Monterey Teams with eASIC to Provide Core-Centric Hierarchical Design Solution
eASICores Combine with Monterey's System-Driven Physical Design Tools to Raise the Level of Physical Abstraction
SUNNYVALE, Calif.--(BUSINESS WIRE)--Jan. 11, 2002--
Monterey Design Systems and eASIC Corporation today announced a
strategic agreement to provide the industry's first core-centric
hierarchical design solution.
The combination of eASIC's eASICore® configurable cores and
Monterey's System-Driven Physical Design(TM) solution raises the level
of physical design abstraction providing dramatic improvements in
designer productivity and turnaround time. Engineers at Monterey and
eASIC have been working together over the past year to develop a
core-based design environment that yields significant productivity
gains for large ASIC and SoC designs.
"Monterey's hierarchical methodology fits in very well with our
approach of providing configurable cores for use as the basic building
blocks of complex IC designs," said Ze'ev Wurman, Vice President of
Software at eASIC. "We believe that the deployment of eASICores in
conjunction with Monterey design tools will enable our customers to
realize the goals of high-performance, rapid turnaround time, and low
cost for their mission critical IC designs."
"eASICore is an ideal complement to Monterey's hierarchical
methodology that uses complex cores as building blocks for
multi-million gate SoC designs," said Dave Reed, Vice President of
Marketing and Solutions Delivery for Monterey. "eASIC provides the
building blocks and Monterey the tools to form an unbeatable
combination that enables our customers to thrive in today's
competitive marketplace."
One of the most challenging aspects of intellectual property (IP)
reuse is integration of existing IP cores into a functional chip
design. By developing and packaging an integration environment based
on Monterey's SDPD tools together with eASICores, eASIC provides a
much more complete package than they would otherwise be able to offer.
The inclusion of SDPD tools dramatically reduces the time and effort
required to integrate the configurable cores into complex chip
designs.
About Monterey Design Systems
Monterey Design Systems provides the industry's only System-Driven
Physical Design solution, giving customers the fastest and most
advanced System to GDSII approach for deep sub-micron SoC design. The
company combines design planning, physical prototyping and automated
physical implementation to provide a physical design flow that begins
at the system level and produces a manufacturing ready layout.
Monterey Design Systems is privately held and partners with leading
EDA companies such as Cadence (NYSE:CDN - news) and Synopsys (Nasdaq:SNPS - news) to
ensure interoperability in ASIC and COT design flows. Monterey Design
Systems is located at 894 Ross Drive, Sunnyvale, CA 94089-1443, tel:
1.408.747.7370, fax: 1.408.747.7377, http://www.montereydesign.com/.
About eASIC
eASIC Corporation is pioneering a breakthrough ASIC design
methodology while maintaining standard manufacturing process. The
company is offering a Universal Fabric for IC design along with
configurable logic cores for System-on-Chip and platform-based
designs. eASIC's products allow achieving high performance and density
together with ease-of-design, rapid time-to-market and reduced product
development cost. eASIC Corporation is a privately held company based
in San Jose, California, tel: 408-264-7128. Part of its R&D activity
is performed by its wholly owned design subsidiary in Romania.
http://www.easic.com/.
Note to Editors: Monterey and Monterey Design Systems are
registered trademarks and System-Driven Physical Design is a trademark
of Monterey Design Systems. All other trademarks and registered
trademarks are the property of their respective owners.
Contact:
Monterey Design Systems, Sunnyvale
Cedric Iwashina, 408/747-7370
cedric@aristotech.com
or
Lee Public Relations
Barbara Marker, 503/209-2323
barbara@leepr.com
or
eASIC
Ze'ev Wurman, 408/264-7128
zeev@easic.com
